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1 SP5848 preliminary information features dual independent pll frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application 2.2ghz up-synthesiser optimised for low phase noise up to comparison frequencies of 4mhz 1.3ghz down-synthesiser optimised for low phase noise and small step size common reference oscillator and divider with independently selectable ratios for each synthesiser 10:1 programmable charge pump current ratio in up synthesiser 3-wire bus programmable, each synthesiser indepently addressable low power consumption, typ 100mw at 5v esd protection, (normal esd handling procedures should be observed) applications tv, vcr, and cable tuning systems description the SP5848 is a dual pll frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners. each synthesiser loop within the SP5848 is independently addressable and contains an rf programmable divider, phase/frequency detector and charge pump/loop amplifier section; a common reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable. both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low comparison frequency. rf1 input 16/17 4 bit count 11 bit count 15 bit latch 2 bit latch port p0 pump 1 drive 1 16 bit latch data clock enable 2 data interface rf 2 input 16/17 4 bit count 12 bit count 1 bit latch 2 bit latch 5 bit latch 9 divide port p1 pump 2 drive 2 figure 1 - block diagram ds5076 issue 1.6 october 1999 ordering information SP5848/kg/qp1s SP5848/kg/qp1t SP5848 2.2/1.3ghz 3-wire bus dual low phase noise pll preliminary information
2 SP5848 preliminary information electrical characteristics t amb = -40 o c to +80 o c , vcc = 4.5 to 5.5 v, these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. figure 2 - pin connections qp20 port p1 charge pump 2 drive 2 vee 2 rf2 input rf2 input vcc2 crystal crystal cap vee port p0 charge pump 1 drive 1 vee 1 rf1 input rf1 input vcc1 enable data clock characteristic pin value units conditions min typ max supply voltage 7, 14 4.5 5.5 v supply current 18 22 ma synthesiser 1 (up) rf1 input voltage 15,16 40 300 mv rms 80 -2200mhz rf1 input impedance 15,16 see figure 4 rf1 division ratio 240 32767 reference division 1 see table 1 ratio comparison frequency 1 4 mhz equivalent phase noise -148 dbc/hz ssb, within loop bandwidth, all at phase detector 1 comparison frequencies charge pump 1 output 19 see table 3 current vpin 19=2v charge pump 1 output 19 3 10 na vpin19 = 2v leakage charge pump 1 drive 18 0.5 ma vpin 18 = 0.7v output current
3 SP5848 preliminary information electrical characteristics (continued) t amb = -40 o c to +80 o c , vcc = 4.5 to 5.5 v, these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. characteristic pin value units conditions min typ max synthesiser 2 (down) rf2 input voltage 5,6 30 300 mv rms 80 -1300mhz rf2 input impedance 5,6 see figure 5 rf2 division ratio 240 65535 reference division 2 see table 2 ratio comparison frequency 2 16.25 4000 khz phase noise degrades above 250khz equivalent phase noise -144 dbc/hz ssb, within loop bandwidth, all at phase detector 2 comparison frequencie up to 250khz charge pump 2 output 2 see table 4 current vpin 2=2v charge pump 2 output 2 3 10 na vpin2 = 2v leakage charge pump 2 drive 3 0.5 ma vpin 3 = 0.7v output curent data, clock and enable 12,11,13 input high voltage 3 vcc v input low voltage 0 0.7 v input current -10 10 a all input conditions hysterysis 0.8 vpp clock rate 11 500 khz bus timing - data set up 300 ns data hold 600 ns enable setup 300 ns enable hold 600 ns clock to enable 300 ns reference oscillator crystal frequency 8, 9 2 16 mhz see figure 6 for application external reference input 8 2 20 mhz sinewave coupled through frequency 10nf blocking capacitor external reference drive 8 0.2 0.5 vpp sinewave coupled through 10nf blocking capacitor outputs ports p0 - p1 1, 20 see note 1 sink current 2 ma vport = 0.7v leakage current 10 a vport = vcc note 1 output ports high impedance on power up, with data, clock and enable at logic 0
4 SP5848 preliminary information absolute maximum ratings all voltages referred to vee at 0v characteristic value conditions min max units supply voltages -0.3 7 v rf1 input voltage 2.5 vp-p differential rf2 input voltage 2.5 vp-p differential all i/o ports dc offset -0.3 vcc+0.3 v storage temperature -55 +125 c junction temperature 150 c package thermal resistance chip to ambient 100 c/w chip to case 30 c/w power consumption with all 121 mw all ports off vcc =5.5v esd protection 2 kv mil std 883 latest revision methood 3015 class 1 functional description the SP5848 contains two pll frequency synthesiser loops, each independently programmable from a 3-wire bus. the device is optimised for application in double conversion tuners where synthesiser 1 would form part of the upconverter and synthesiser 2 part of the down converter. both loops are optimised for application in low phase noise loops and furtherly synthesiser 2 offers low comparison frequencies. a block diagram is contained in figure 1. the device is programmed via a 3-wire bus where data is fed on serial data and clock lines and is gated by an enable line. figure 3 indicates the format of the data. the sequence and timing of data load is described below in ?rogramming mode?description. each synthesiser is independently addressable and is defined by the lsb bit within the data transmission. a common reference frequency source and reference divider is used to derive the comparison frequency for both pll loops. the reference division ratio is programmable via the data bus as defined in tables1 and 2. the charge pump current for each loop is also programmable via the data bus as defined in tables 3 and 4 two switching ports are provided to control switching functions within the tuner. these ports also access test signals within the pll as defined in figure 7. ports power up in high impedance state. programming mode the SP5848 is designed to be programmed from a standard 3-wire bus consisting of clock, data and enable, where the serial clock and data lines can be shared with other devices and the enable line is a unique line for individual device selection. to simplify programming each synthesiser is independently addressed, with the required loop being selected by the lsb bit , which functions as the address, therefore to fully program the device two complete data transmissions must be sent. the data format for each transmission is contained in figure 3. test modes as described in figure 7, can be invoked by setting bit t0 in synthesiser 2 data word to a ??and sending control data for bits t1-t2. in normal operation where t0 is set to a ??bits t1 and t2 do not need to be transmitted
5 SP5848 preliminary information 2 22 2 21 2 20 2 19 2 18 2 17 2 16 2 15 2 1 2 0 clock enable data p1 p0 cu1 cu 0 ru2 ru1 ru0 msb lsb ? frequency data (15 bits) synthesiser 1 control data clock enable data 2 24 2 23 2 22 2 20 2 19 2 18 2 17 2 16 2 1 2 0 t2 t1 t0 cd rd2 rd1 rd0 msb lsb 1 frequency data (16 bits) synthesiser 2 control data cu0 - cu1 : synthesiser 1 charge pump ru0 - ru2 : synthesiser 1 reference division ration cd : synthesiser 2 charge pump rd0 - rd2 : synthesiser 2 reference division ratio t0 - t2 : test modes p0 - p1 : switching ports p0 - p1 figure 3 - control data
6 SP5848 preliminary information figure 4 - synthesiser 1 rf input impedance j2 j1 j0.5 j0.2 0 2 j0.2 2 j0.5 2 j1 2 j2 1 0.5 0.2 j5 2 j5 2 5 80mhz 1ghz 2 2ghz 1 7ghz figure 5 - synthesiser 2 rf input impedance j2 j1 j0.5 j0.2 0 2 j0.2 2 j0.5 2 j1 2 j2 1 0.5 0.2 j5 2 j5 2 5 80mhz 1 3ghz 0 5ghz 0 9ghz
7 SP5848 preliminary information table 1 - synthesiser 1 reference division ratio ru2 ru1 ru0 ratio 0002 0014 0108 01116 10032 10164 110128 111256 table 2 - synthesiser 2 reference division ratio ru2 ru1 ru0 ratio 00 04 00 18 01 016 01 132 10 064 1 0 1 128 1 1 0 256 1 1 1 512 table 3 - synthesiser 1 charge pump current cu1 cu0 current (typical in ma) 0 0 0.12 0 1 0.26 1 0 0.55 1 1 1.2
8 SP5848 preliminary information table 4 - synthesiser 2 charge pump current figure 6 - crystal oscillator application cd current (typical in ma) 0 0.05 1 0.2 t2 t1 t0 functional description x x 0 normal operation 0 0 1 both charge pumps in sink mode 0 1 1 both charge pumps in source mode 1 0 1 port p1 = fcomp1, p0 = fcomp2 and charge pumps disabled 1 1 1 port p1 = (fpd1)/2, p0 = (fpd2)/2 x = dont care figure 7 - test modes
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